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Chaithanya Naik Mude

Scaling Multi-Level Superconducting Qubit Readout with ML

218 words·2 mins

Fast, accurate qubit readout is a bottleneck for scaling superconducting quantum computers. This line of work designs hardware-efficient machine-learning readout architectures that fit on FPGA-class control hardware and extend to multi-level (qutrit+) readout.

Key results
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  • 16% relative improvement in readout accuracy by identifying relaxations that occur during readout (ISCA 2023).
  • Matched-filter architecture using less than 8% of FPGA resources.
  • 6.6% relative accuracy improvement for multi-level readout with better leakage detection during readout (DAC 2025).

Papers
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Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu. DAC 2025. [Paper]

Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures Satvik Maurya, Chaithanya Naik Mude, William D. Oliver, Benjamin Lienhard, Swamit Tannu. ISCA 2023. [Paper]

Code
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Code available upon request — public release coming soon.

BibTeX
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@inproceedings{mude2025multilevel,
  title     = {Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout},
  author    = {Mude, Chaithanya Naik and Maurya, Satvik and Lienhard, Benjamin and Tannu, Swamit},
  booktitle = {62nd Design Automation Conference (DAC)},
  year      = {2025}
}

@inproceedings{maurya2023scaling,
  title     = {Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures},
  author    = {Maurya, Satvik and Mude, Chaithanya Naik and Oliver, William D. and Lienhard, Benjamin and Tannu, Swamit},
  booktitle = {50th International Symposium on Computer Architecture (ISCA)},
  year      = {2023},
  doi       = {10.1145/3579371.3589042}
}